1. Field of the Invention
The present invention is directed to a large scale integrable memory cell including the combination of a field effect transistor and a capacitor associated with a trench formed in a semiconductor substrate.
2. Description of the Prior Art
A memory cell of the type with which the present invention is concerned is generally shown in the IEEE Journal of Solid State Circuits, Volume SC-21, No. 5, October 1986, pages 605-611, particularly FIG. 1. The planar, active region of the memory cell adjacent to the trench in the lateral direction encompasses the entire trench edge so that the lateral limitation of the trench lies inside the lateral limitation of the active region while providing an adjustment spacing. With the adjustment spacing, after the placement of the active region of the memory cell on the semiconductor body, the position of a mask which defines the lateral limits of the trench can differ from its intended position by an amount which is smaller than the adjustment spacing without the storage capacitance being increased by the trench wall deviating too far from its rated value. The adjustment spacing between the trench edge and the lateral limitation of the active region, however, causes an increase in the area requirement for the memory cell.